Time-division multiplexed (TDM) switch fabrics are utilized in a variety of network applications for switching Optical Transport Network (OTN), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Ethernet, and the like. Numerous challenges exist in designing next generation time-division multiplexed (TDM) switch fabrics realized in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other integrated circuits. For example, design challenges include increasing fabric switching capacity, increasing the line rate of the interconnections within the switch fabric, and increasing the level of system-on-chip (SOC) integration (e.g., by incorporating a packet switch, or another independent function, in the ASIC together with the TDM switch). Conventionally, a time-space switch and a packet switch are realized in separate devices, e.g. different ASICs.
A time-space switch has N input links of TDM data divided into M timeslots. Each of the N output links can select any of the M timeslots from any of the N input links. Each output pair (mout, nout) can select from any of the input pairs (min, nin) without blocking. The capacity (or throughput) of a time-space switch is a function of (a) the number of links, N, and (b) the throughput (or bit rate) of each link. As the capacity of networks increase, so do the requirements of the switching equipment used in these networks. By consequence, the trend in switching equipment is towards systems that support higher link rates, as well as a larger number of links. The techniques and methods used to implement these systems need to accommodate scalability accordingly. In today's electronic systems it is common to transfer digital data between components using high speed serial (HSS) links. In order for these high speed serial links to be reliable, a physical layer encoding scheme is typically required. Physical layer encoding is required to ensure sufficient transition density and DC balance for receivers to recover the signal. Encoding may also be required to correct for errors introduced in transmission. Physical layer encoding addresses these issues by transforming the transmitted data in a systematic fashion and, as necessary, adding a specified amount of redundancy. With prior knowledge of the encoding scheme used at the transmitter, the receiver can make use of this information to improve the integrity of the received data. However, a fundamental tradeoff exists between maximizing the degree of improved reliability, while minimizing the amount of additional overhead (redundancy) that is added at the transmitter.
Conventionally, there is a lack of a unified encoding standard that is universal in switch system applications. The most common standard encoding scheme used for serial links that are driven across system backplanes is 8B/10B. With this scheme, the serial transmit data is transformed into a sequence of discrete control characters and data characters. Special control characters are used to delineate the start and end of packets, and the idle regions between packets. The interface to a time-space switch may also use the control characters to delineate and synchronize switch frames launched into the switch fabric. The 8B/10B protocol is engineered to offer good transition density and DC balance, albeit at the expense of an additional 25% of overhead (since 2 bits are added to every 8-bit input character to derive a 10-bit output character). Furthermore, the 8B/10B does not offer any error correction capacity, which has become a requirement for reliable data integrity as link speeds increase. As such, additional overhead is required on top of 8B/10B to add Forward Error Correction (FEC).
Once the framed serial data is reliably received, a simple timeslot interchanger (TSI) switch can be implemented by writing timeslot values into a Random Access Memory (RAM) and then reading output values in a new order. Other methods include writing the timeslot data into registers and using multiplexers to select the order of the output timeslots. Adding more input and output links introduces a spatial dimension to the timeslot interchanger and results in a time-space switch. Each output link may select any timeslot from any input link for each output timeslot. However, interconnect complexity increases exponentially as the spatial dimension grows, resulting in long high fan-out nets which make it difficult to route and meet the high-speed timing constraints. By consequence, traditional implementation methods break down as the size of the switch grows, and alternative techniques are required to achieve the necessary scalability for today's systems.